This invention relates to simulation and more particularly to simulation of digital circuits.
In the simulation of digital circuits, the designer of digital circuits has designed a particular digital circuit for an expected behavior of the digital circuit. These designer during the design process should verify the actual behavior of the digital circuit with the expected behavior of the digital circuit. This verification can be accomplished through the use of simulation. The designer may provide an input and input pattern sequence for the digital circuit to a simulator in order to test the digital circuit. Simulation has long been an essential step in the design and manufacture of circuits.
Accordingly, many simulators have been developed and marketed. One widely used circuit simulator is a program which has been developed at the Electronics Research Laboratory of University of California, Berkley, known as SPICE. In general, SPICE is a system for simulating non-linear circuits in time using non-linear time-independent generalized admittance representations. A popular version of SPICE (SPICE 2) is described xe2x80x9cSPICE Version 2G.6 User""s Guide xe2x80x9cBerkley-University of California, Department of Electrical Engineering and Computer Science, 1980 by Vladimirescu, et al.xe2x80x9d incorporated herein by reference in its entirety.
Circuit simulators are typically software based and are designed to accept a description of the circuit which defines the circuit topology and element values. Each element in the circuit is typically specified by an element line containing the element name, the connecting node and the electrical parameter values. Simulators typically simulate circuitries which include passive devices such as resistors, capacitors, diodes, inductors and mutual inductors, stimuli, such as voltage and current sources and active devices such as bipolar junction transistors (BJT), junction field effect transistors (JFET) and metal oxide semiconductor field effect transistors (MOSFET). The simulator can typically be configured to perform DC analysis, AC small signal analysis and transient analysis. SPICE is descendant of a simulator known as Cancer, L. W. Nagel and R. A. Rohrer xe2x80x9cComputer Analysis of Non-Linear Circuits, Excluding Radiation (Cancer)xe2x80x9d IEEE J. Solid-State Circuits, Volume SC-6, page 166-182 (August, 1971). Additionally, incorporated herein by reference in their entirety. SPICE and other integrated circuits simulators typically include a lumped parameter characterization of ideal components used in an integrated circuit. These include passive components such as resistors, inductors and capacitors. Active components may be provided by models which include a specification of various structural feature and parameters that affect their operation. After the design of the circuit, the designer typically generates at a keyboard input to a computer, a line of code which specifies each device in the circuit. The active devices are typically specified by an identifying number, a set of node numbers which identify the circuit nodes to which the device terminals are attached, whether the device is a N or P type, the device width and length and model assigned to simulate operation of the device. The model assigned to simulate a particular device depends on several factors. First, if the device is connected to a power supply or a ground node, a different model may be selected if the device is not so connected. Secondly, some models are suitable for modeling P type devices where as other devices are designed to model N type devices. Finally, a particular model is typically suitable only for devices given a given size range. Thus, the circuit designer is faced with designing a particular model for each device in the circuit. This prevents a tedious task for an integrated circuit having several thousand active devices.
Data specifying a particular model is referred to a model card, while data specifying a particular device is referred to a device card. Each set of data includes a line of code as a listing. Such nomenclature stems from the days when punched computer cards contained the data necessary for each specified model or device. All of the device cards and model cards are referred to collectively as a SPICE deck. The model cards are developed by empirical testing of a physical device and may be used in simulations and different circuits made with similar processes. The device cards are typically hand coded, for example data is entered at a keyboard for a particular circuit design. When the SPICE deck is loaded into a computer program with an electronic circuit simulator, the computer simulates operation of the circuit.
However, the simulation of digital circuits using SPICE is time consuming, especially for large designs of these digital circuits and in the library cell characterization of these circuits. To characterize a typical digital library cell, hundreds of SPICE runs are required to provide for power supply, slew rate, temperature and load variations. The behavior of digital circuits in terms of its input and output patterns are generally known, but the minimum time required for the outputs to settle to a steady state value in order to change the inputs for the next output is not known. To utilize a standard SPICE stack that will run all the required variations, the simulation time or bit time is generally over estimated by the designer. By employing this over-estimation, the designer is reasonably confident that all of the simulations will be correctly run to the completion. This method of operating SPICE results in many undesirable problems. The time to use the SPICE program with these large designs will take an unnecessarily large amount of time if a overly large bit time is given since the large bit time is unnecessary for every SPICE run. An accurate estimate of the time required for the output of these digital circuits to settle to a steady state value, resulting from a change in input, has to be determined accurately in order to save time. If the selected bit time is small, the outputs may not settle within the selected bit time, and a rerun of the SPICE program with the same input may be required with a larger bit time. In these cases the entire time that the run has been taken has been lost. Additionally, the outputs of these digital circuits may not settle at all due to an unforeseen problem, and a rerun with a larger bit time may be required in order to establish this problem. Needless to say, each of these runs requires CPU time, and CPU time may be wasted while waiting unnecessarily for a long bit time if the output of the digital circuit has already settled.
An additional problem with a long bit time is redundancy. Data may be generated by SPICE in the form of punch files as the SPICE program simulates every time point during the SPICE run. This data may extend into a time period that is beyond the interest of the designer, resulting in data that is unnecessary.
Standard cell libraries include information corresponding to primitive gates such as an AND, OR, NAND, NOR flip-flops, etc. These circuits are simulated under varying conditions including strong, nominal and weak process variations, for example 4.5 voltage, temperature at 150xc2x0 C., slew (nanoseconds) and load variations (PF). If the time from coding the input patterns to achieving results is too long, submitting these SPICE jobs and analyzing the results may discourage the designer from performing detailed simulation of the cell under all necessary conditions.
The present invention now reduces the simulation time from dependency on the bit time and the estimations based on the bit time. The present invention advantageously schedules the next input bit patterns for the SPICE program immediately when the outputs of the previous SPICE iterations has settled, allowing the designer to reuse the same SPICE deck for simulation involving variations in power supply, temperature slew and load conditions.
The present invention reduces data requirements since the next run of SPICE is scheduled immediately. There is no output of the program other than the output associated with the required run. The idle time that had been spent in waiting for the next set of input conditions has been reduced or eliminated, and consequently, the data produced during this idle time is eliminated. Thus, SPICE punches out a fewer number of less meaningful data points. Thus, processing time on the resulting punch files from SPICE is increased for subsequent programs or filters. The present invention eliminates the need to represent the input waveform as a piecewise linear PWL waveforms, eliminating the timing description associated with these PWL waveforms. The input output behavior can now be described as a predetermined set of patterns, for example, ASCII text.
The present invention provides instantaneous checking of the output. No longer does the entire SPICE run need to be completed when a malfunction has occurred. The present invention detects the malfunction and instantaneously stops execution of the SPICE simulation, saving time. Advantageously, the checking function can be disconnected so that a new circuit having an unknown behavior can be simulated. Furthermore, error messages can be given to the user describing the pin and the pattern on which the malfunction has occurred.
The present invention provides pin-to-pin delays every time when an output transition occurs. This eliminates the needs for post processing of the data. Additionally, the present invention can detect errors in tiling that occurred while the basic functionality of the circuit is correct, which may not be acceptable to a designer. The present invention provides break points in transition regions around signal change ensuring that the transitions are detected and sufficient number of time points are provided to a simulator to compute the delay.